1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic random access memory (RAM).
2. Description of the Related Art
FIG. 8 partially shows a circuit of a conventional semiconductor memory device (one of memory blocks). In FIG. 8, a memory cell array 1, a row decoder 2, a column pre-decoder 90, a column decoder 4, a bit-line pair 31, a data-line pair 32, a switching-element pair 34, and the like are shown. Herein, one bit line of the bit-line pair 31 is indicated by 31A, and the other bit line is indicated by 31B. Similarly, one data line of the data-line pair 32 is indicated by 32A, and the other data line is indicated by 32B. Also, one switching element of the switching-element pair 34 is indicated by 34A, and the other switching element is indicated by 34B. A switching element can also be an N-channel transistor, not being limited to this specific type.
Into the memory block shown in FIG. 8, row addresses and column addresses (CA0-CA7) are input.
The row decoder 2 selectively sets a word line 30 among a plurality of word lines 30 active in accordance with the input row addresses. Herein, the phrase "to set a signal line active" means "to set a signal line into a logically activated state or a selected state, by setting the potential of the signal line to a certain value". Similarly, the phrase "to set a signal line inactive" used herein means "to set a signal line into a logically inactivated state or a non-selected state, by setting the potential of the signal line to another certain value".
The column pre-decoder 90 selectively sets one signal line to be active in each of four signal-line sets (CA01, CA23, CA45, and CA67), in accordance with the input column addresses (CA0-CA7). Each of the signal-line sets consists of four signal lines. Depending on the combination of the signal lines which are selectively set active by the column pre-decoder 90, any one of the 0th to 255th column decoders is selected. A column signal line 47 which is connected to the selected column decoder is set to be active. At this time, a switching-element pair 34 which is connected to the activated column signal line 47 is turned ON, so that the bit-line pair 31 and the data-line pair 32 are electrically connected to each other.
A bit-line precharge signal generating circuit 7 generates a bit-line precharge signal. In response to the bit-line precharge signal, the potential of each of the bit lines 31A and 31B is precharged to 1/2 Vcc, where Vcc represents the power supply potential. The potential of each of the data lines 32A and 32B are precharged to the same potential as that of the bit lines 31A and 31B.
When the bit-line pair 31 is being precharged, a sense amplifier driving signal generating circuit 8 sets both the potentials of a PMOS sense amplifier driving signal line 48 and an NMOS sense amplifier driving signal line 49 to 1/2 Vcc. When a sense amplifier 9 operates, the sense amplifier driving signal generating circuit 8 sets the potential of the PMOS sense amplifier driving signal line 48 to Vcc and the potential of the NMOS sense amplifier driving signal line 49 to GND.
The sense amplifier 9 amplifies the potential difference read from memory cells 33 onto the bit-line pair 31.
A main amplifier 5 amplifies the potential difference of the data-line pair 32. An output circuit 6 outputs a signal for identifying the data stored in the memory cells 33 at an output terminal 35 in accordance with the output of the main amplifier 5.
A timing generating circuit 10 sets signal lines 51-55 to be active at predetermined timings. The signal lines 51-55 are connected to the row decoder 2, the bit-line precharge signal generating circuit 7, the sense amplifier driving signal generating circuit 8, the column pre-decoder 90 and the main amplifier 5, respectively.
FIG. 9 shows an exemplary configuration of the conventional column pre-decoder 90. As is shown in FIG. 9, the column pre-decoder 90 includes four circuits 60, 61, 62, and 63. The circuit 60 selectively sets one of the four signal lines active in the signal-line set CA67, in accordance with the input column addresses CA6 and CA7. The circuit 61 and the circuit 62 are identical with the circuit 60 and operate in the same way as the circuit 60 operates. The circuit 63 selectively sets one of four signal lines active in the signal-line set CA01, in accordance with the input column addresses CA0 and CA1. In this conventional example, the potential of a signal line which is selectively set to be active is the power supply potential (Vcc).
FIG. 10 shows potential variations of various signal lines during the operation of the conventional semiconductor memory device shown in FIG. 8. In FIG. 10, the horizontal axis represents time, and the vertical axis represents voltage. In this conventional example, the data read out from the memory cells 33 is assumed to be at a low level (L).
The timing generating circuit 10 sets the signal line 52 inactive, and the signal lines 51, 53, 54 and 55 active. As a result, as is shown in FIG. 10, the potential of each signal line varies.
When the signal line 52 is set to be inactive, the bit-line precharge signal Generating circuit 7 makes the potential of the bit-line precharge signal to the low level (L).
When the signal line 51 is set to be active, the row decoder 2 selectively makes one word line 30 active, in accordance with the input row addresses.
When the signal line 53 is set to be active, the sense amplifier driving signal generating circuit 8 changes the potential of the PMOS sense amplifier driving signal line 48 from 1/2 Vcc to Vcc (power supply potential), and also changes the potential of the NMOS sense amplifier driving signal line 49 from 1/2 Vcc to GND.
When the signal line 54 is set to be active, the column pre-decoder 90 selectively makes one of four signal lines active in the signal-line set CA01, in accordance with the input column addresses (CA0-CA7). As described above, one of the four signal lines of each of the other three signal-line sets (CA23, CA45, and CA67) has already been selectively set to be active. The potentials of the signal lines which are selectively set to be active are the power supply potential (Vcc), as is apparent from FIG. 9.
At the same time when one signal line in the signal-line set CA01 is selectively set to be active, the column decoder 4 sets a column signal line 47 active, depending on the combination of the signal lines which are selectively set to be active by the column pre-decoder 90. The potential of the active column signal line 47 is the power supply potential (Vcc), the same as the potentials of the signal lines which are selectively set to be active in the signal-line sets (CA01, CA23, CA45, and CA67). As a result, the switching-element pair 34 which is connected to the column signal line 47 is turned ON, so that the bit-line pair 31 and the data-line pair 32 are electrically connected to each other.
When the signal line 55 is set to be active, the main amplifier 5 amplifies the potential difference which is transmitted to the data-line pair 32.
Generally, the capacitances of the data lines 32A and 32B are several times as large as the capacitances of the bit lines 31A and 31B. Accordingly, in the above conventional semiconductor memory device, when the bit-line pair 31 and the data-line pair 32 are connected via the switching-element pair 34 by the active column signal line 47, the potential difference of the bit-line pair 31 decreases, as is shown in FIG. 10.
There may occur a case where a column signal line 47 is set to be active by the column select signal before the potential difference of the bit-line pair 31 is sufficiently amplified, because the adjustment of the timing generating circuit 10 is insufficient, or because the power supply voltage fluctuates. Accordingly, as is shown in FIG. 11, the data of the bit-line pair 31 may possibly be inverted, when the bit-line pair 31 and the data-line pair 32 are electrically connected to each other. As a result, the data to be output to the data-line pair 32 is also inverted, which causes an error.